The present invention relates to a driving apparatus of a semiconductor element, and in particular, to a driving apparatus and its control method for suppressing an over-voltage generated at a transient time when a semiconductor element conducts or interrupts a current.
In electric power conversion systems such as electric automobiles or the like, using a battery as a power supply, an electric power conversion device such as an inverter is provided between a battery and a load (motor, etc.), and as a power semiconductor element used in the power conversion device, a power MOSFET is used when the voltage is low, and an IGBT is used when the voltage is high. The power MOSFET and the IGBT are both voltage drive type elements, and it is desirable to further reduce the on resistance from the need to achieve lower loss. In the voltage drive type power semiconductor element, its on resistance is determined by the sum of a resistance of a channel portion which is formed near the surface of the element and which limits a current according to a gate voltage, and a resistance of a semiconductor substrate portion which forms a depletion layer at an off time of the element. The resistance of the channel portion can be reduced by making the structure finer, but the resistance of the substrate portion is determined by the withstand voltage of the element, and it is impossible to reduce the resistance without reducing the voltage applied to the element at the off time. On the other hand, even if it is intended to reduce the voltage by reducing the voltage of the power supply, if the electric power supplied to the load is constant, the current flows through the element will increase conversely. In this case, since a large current is interrupted at a fast speed, it will result in an increase in the surge voltage (or, it is called as a spike voltage). Thus, it is considered to reduce the transient withstand voltage of the element by suppressing the surge voltage by countermeasures relying on circuits such as a snapper circuit, a gate driving circuit, etc.
As an example of a circuit technique for suppressing the surge voltage generated at the time when the element is turned on or turned off, a driving circuit is disclosed in JP-A-6-291631. This circuit detects a voltage between an input and an output terminal of a voltage drive type power semiconductor element, and the gate resistance is varied according to this detected value, thereby to make slow the speed at which the gate voltage of the element increases or decreases. The voltage drive type power semiconductor element has a saturation characteristic which limits a current conductable by the gate voltage, and when the increase or decrease in the gate voltage is suppressed, the switching speed of the current is also moderated. A parasitic capacitance is included between respective terminals, and in particular, the feedback capacitance between the input terminal and the gate terminal is limited at the transient time in its charging or discharging time due to the gate current. Accordingly, in the prior art technique mentioned above, this property is utilized, and a voltage change (dV/dt) at the time of switching is also moderated. In this manner, when a current change (di/dt), or the voltage change (dV/dt) is moderated, a surge voltage which is caused by the di/dt, and dV/dt is also reduced. In JP-A-6-291631, the gate voltage is detected together with a voltage between the input and output terminals, and a means for changing the gate resistance according to this detected result is also described. An article related to this prior art technique is described in Proceedings of National Conference of Institute of Electrical Engineers, Industrial Application Group, No. 88, "Study of Soft Switching Gate Driving circuit for driving IGBT", 1995. In the driving circuit described in this article, at the time of turn off, first, the voltage between the input and output terminals of the switching element is detected, and the gate resistance is changed from a small value to a large value. Subsequently, the gate voltage is detected, and the gate resistance is changed from a large value to a small value. It is reported that although the surge voltage at the time of switching was suppressed owing to this driving circuit, the overlapping period between a voltage and a current waveform becomes long at the on and off time, and as compared with the case where the prior art gate driving circuit is used, the switching loss is increased to a great extent.
In order to explain the problems in the prior art technique mentioned above, the turn off operation of the voltage drive type power semiconductor element is divided into four periods. Here, the object is an inductive load such as a motor.
(1) gate voltage discharge period: In this period, upon application of an off signal, a gate current flows through a resistance, and electric charge accumulated on the gate is discharged. The gate voltage is decreased with time in accordance with an exponential function having a time constant corresponding to the product of a gate capacitance and a resistance. During this period, a main current and a voltage between the input and output terminals are maintained at values at the on time. PA0 (2) voltage rise period: In this period, the element enters into a saturation operation, and the feedback capacitance is charged by a gate current, and the voltage between the input and output terminals is increased depending on the degree of charging. Since the gate current is used to charge the feedback capacitance, the gate voltage is substantially at a constant value. Since the feedback capacitance has a voltage dependent property, and decreases according to the voltage between the input and output terminals, the voltage increase between the input and output terminals becomes fast from the halfway. PA0 (3) current fall period: From the time point at which the voltage between the input and output terminals reaches the power supply voltage, the main current begins decreasing. A period from the start of decreasing of the main current until it becomes completely zero, is called as the current fall period. The gate voltage decreases again from the finish time point of the feedback capacitance charge period, and the main current decreases according to an instantaneous value of this gate voltage. PA0 (4) off steady period: In this period, the gate voltage decreases to a threshold value or below, and the power semiconductor element is maintained at a state which interrupts the current.
In the case of the prior art technique mentioned above, the gate resistance value is made small during the gate voltage discharge period, and the gate resistance value is increased by detecting at the halfway of the voltage rise period that the voltage between the input and output terminals is increased. And during the voltage rise period and the current fall period, the gate resistance value is maintained at a large value. Then, the gate resistance is made to be a small value again by determining that the element has entered into the off steady state by detecting the gate voltage that this value reached the threshold value or lower.
In a general gate driving circuit, the gate resistance is small and at a constant value from the start of the gate voltage discharge period until the finish of the off steady period, and the voltage rise period and the current fall period are short at respectively several tens to several hundreds of nano seconds (ns). On the other hand, in the prior art technique mentioned above, when the gate resistance value changes from a small value to a large value during the voltage rise period, the voltage rise period and the current fall period are respectively extended to about one to several microseconds (.mu.s). However, if a time delay is caused in the detection or operation, the operation to increase the gate resistance from the small value to the large value will not be performed in good time. In this case, since the current is interrupted in the state in which the gate resistance is small, the surge voltage is caused by a current change (di/dt). Thus, it is a first problem that there is a situation wherein the surge voltage cannot be suppressed.
A second problem is an increase in the delay time. Assuming that the frequency of a carrier wave of an inverter of the PWM (pulse width modulation) control type is several kHz, the non-lap time of upper and lower elements of the inverter has generally an upper limit of 5 .mu.s (miroseconds), and as described above, the voltage rise time alone, it takes 3 to 5 us, and the PWM control becomes unsuitable.
The switching loss is increased due to the increase in the gate resistance value from the voltage rise period to the current fall period, however, it is a third problem to reduce the switching loss as far as possible while suppressing the surge voltage.
Furthermore, against the inductive load, a return diode is provided between the input and output terminals of the power semiconductor element, however, it was difficult to suppress the surge voltage at the time of reverse recovery of this diode.